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(parent: 7c4dc44) | patch
cache: coherence protocol enhancements & bug fixes
authorSteve Reinhardt <steve.reinhardt@amd.com>
Thu, 9 Sep 2010 18:40:18 +0000 (14:40 -0400)
committerSteve Reinhardt <steve.reinhardt@amd.com>
Thu, 9 Sep 2010 18:40:18 +0000 (14:40 -0400)
commit71aca6d29e686ecdec2828c8be1989f74d9b28d3
tree1ff5b36c08f5e1c3853208674608d141e2924c57tree
parent7c4dc4491a6367888154129d2799b5f564ecb0d9commit | diff
cache: coherence protocol enhancements & bug fixes
Allow lower-level caches (e.g., L2 or L3) to pass exclusive
copies to higher levels (e.g., L1).  This eliminates a lot
of unnecessary upgrade transactions on read-write sequences
to non-shared data.

Also some cleanup of MSHR coherence handling and multiple
bug fixes.
src/mem/cache/base.hh diff | blob | history
src/mem/cache/cache.hh diff | blob | history
src/mem/cache/cache_impl.hh diff | blob | history
src/mem/cache/mshr.cc diff | blob | history
src/mem/cache/mshr.hh diff | blob | history
src/mem/cache/mshr_queue.cc diff | blob | history
src/mem/cache/mshr_queue.hh diff | blob | history