fhdl/verilog: lower complex slices before reset insertion
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Sun, 30 Jun 2013 12:32:47 +0000 (14:32 +0200)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Sun, 30 Jun 2013 12:32:47 +0000 (14:32 +0200)
commit71b89e4c46e5487e995f6de6f2d1cb478479264c
treea83a342db263ec8348a12020cce02cc6563631a0
parentded5e569ebbf4927c04f9be5194e20393546ea44
fhdl/verilog: lower complex slices before reset insertion
migen/fhdl/verilog.py