Fix tests; Remove simulation;
authorSergeyDegtyar <sndegtyar@gmail.com>
Tue, 20 Aug 2019 12:52:25 +0000 (15:52 +0300)
committerSergeyDegtyar <sndegtyar@gmail.com>
Tue, 20 Aug 2019 12:52:25 +0000 (15:52 +0300)
commit71dd412ac55860cbf51d91d26088515978f70116
treec13ac7fde357fd1a4c0ff485a3c66bcdc40bfdca
parent153ec0541c17ee8fad093c002a2724bc33dfe4b9
Fix tests; Remove simulation;

- Add -map and -assert options for equiv_opt;
!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
- dffs;
- div_mod;
- latches;
- mul_pow;
- Add design -load;
- Remove simulations;
34 files changed:
tests/ice40/add_sub.v [new file with mode: 0644]
tests/ice40/add_sub.ys
tests/ice40/add_sub_tb.v [deleted file]
tests/ice40/add_sub_top.v [deleted file]
tests/ice40/common.v [deleted file]
tests/ice40/dffs.v [new file with mode: 0644]
tests/ice40/dffs.ys
tests/ice40/dffs_tb.v [deleted file]
tests/ice40/dffs_top.v [deleted file]
tests/ice40/div_mod.v [new file with mode: 0644]
tests/ice40/div_mod.ys
tests/ice40/div_mod_tb.v [deleted file]
tests/ice40/div_mod_top.v [deleted file]
tests/ice40/latches.v [new file with mode: 0644]
tests/ice40/latches.ys
tests/ice40/latches_tb.v [deleted file]
tests/ice40/latches_top.v [deleted file]
tests/ice40/memory.v [new file with mode: 0644]
tests/ice40/memory.ys
tests/ice40/memory_tb.v [deleted file]
tests/ice40/memory_top.v [deleted file]
tests/ice40/mul_pow.v [new file with mode: 0644]
tests/ice40/mul_pow.ys
tests/ice40/mul_pow_tb.v [deleted file]
tests/ice40/mul_pow_top.v [deleted file]
tests/ice40/mux.v [new file with mode: 0644]
tests/ice40/mux.ys
tests/ice40/mux_tb.v [deleted file]
tests/ice40/mux_top.v [deleted file]
tests/ice40/run-test.sh
tests/ice40/tribuf.v [new file with mode: 0644]
tests/ice40/tribuf.ys
tests/ice40/tribuf_tb.v [deleted file]
tests/ice40/tribuf_top.v [deleted file]