Merge pull request #976 from YosysHQ/clifford/fix974
authorClifford Wolf <clifford@clifford.at>
Fri, 3 May 2019 13:29:44 +0000 (15:29 +0200)
committerGitHub <noreply@github.com>
Fri, 3 May 2019 13:29:44 +0000 (15:29 +0200)
commit71ede7cb05ae35c90eccb80ffc413b4559ba7e60
tree73229c3e02655a9fd3c9f2bb987f44b226d65fc7
parent97423caddaafa0fbaca6f541a9c3e17f036b198b
parent6bbe2fdbf32e6335cdbecc21547e54992c3a606d
Merge pull request #976 from YosysHQ/clifford/fix974

Fix width detection of memory access with bit slice