Fixing old e-mail addresses and deadnames
authorClaire Xenia Wolf <claire@clairexen.net>
Mon, 7 Jun 2021 22:39:36 +0000 (00:39 +0200)
committerClaire Xenia Wolf <claire@clairexen.net>
Mon, 7 Jun 2021 22:39:36 +0000 (00:39 +0200)
commit72787f52fc31954e4b7dc3dc34d86705fc4e9dd1
treeae771b020306e70d155344cab991773c363bb3bc
parente65ed3f228bd0e26248eaaeabdcea507379d757a
Fixing old e-mail addresses and deadnames

s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
309 files changed:
COPYING
Makefile
README.md
backends/aiger/aiger.cc
backends/aiger/xaiger.cc
backends/blif/blif.cc
backends/btor/btor.cc
backends/edif/edif.cc
backends/firrtl/firrtl.cc
backends/intersynth/intersynth.cc
backends/json/json.cc
backends/protobuf/protobuf.cc
backends/rtlil/rtlil_backend.cc
backends/rtlil/rtlil_backend.h
backends/simplec/simplec.cc
backends/smt2/smt2.cc
backends/smt2/smtbmc.py
backends/smt2/smtio.py
backends/smv/smv.cc
backends/spice/spice.cc
backends/table/table.cc
backends/verilog/verilog_backend.cc
frontends/aiger/aigerparse.cc
frontends/aiger/aigerparse.h
frontends/ast/ast.cc
frontends/ast/ast.h
frontends/ast/dpicall.cc
frontends/ast/genrtlil.cc
frontends/ast/simplify.cc
frontends/blif/blifparse.cc
frontends/blif/blifparse.h
frontends/json/jsonparse.cc
frontends/liberty/liberty.cc
frontends/rtlil/rtlil_frontend.cc
frontends/rtlil/rtlil_frontend.h
frontends/rtlil/rtlil_lexer.l
frontends/rtlil/rtlil_parser.y
frontends/verific/verific.cc
frontends/verific/verific.h
frontends/verific/verificsva.cc
frontends/verilog/const2ast.cc
frontends/verilog/preproc.cc
frontends/verilog/preproc.h
frontends/verilog/verilog_frontend.cc
frontends/verilog/verilog_frontend.h
frontends/verilog/verilog_lexer.l
frontends/verilog/verilog_parser.y
guidelines/CodeOfConduct
guidelines/Windows
kernel/bitpattern.h
kernel/calc.cc
kernel/cellaigs.cc
kernel/cellaigs.h
kernel/celledges.cc
kernel/celledges.h
kernel/celltypes.h
kernel/consteval.h
kernel/cost.h
kernel/driver.cc
kernel/hashlib.h
kernel/log.cc
kernel/log.h
kernel/macc.h
kernel/modtools.h
kernel/register.cc
kernel/register.h
kernel/rtlil.cc
kernel/rtlil.h
kernel/satgen.cc
kernel/satgen.h
kernel/sigtools.h
kernel/timinginfo.h
kernel/utils.h
kernel/yosys.cc
kernel/yosys.h
libs/bigint/README
libs/ezsat/README
libs/ezsat/demo_bit.cc
libs/ezsat/demo_cmp.cc
libs/ezsat/demo_vec.cc
libs/ezsat/ezminisat.cc
libs/ezsat/ezminisat.h
libs/ezsat/ezsat.cc
libs/ezsat/ezsat.h
libs/ezsat/puzzle3d.cc
libs/ezsat/testbench.cc
libs/subcircuit/README
libs/subcircuit/subcircuit.cc
libs/subcircuit/subcircuit.h
manual/APPNOTE_010_Verilog_to_BLIF.tex
manual/APPNOTE_011_Design_Investigation.tex
manual/APPNOTE_012_Verilog_to_BTOR.tex
manual/CHAPTER_StateOfTheArt/simlib_yosys.v
manual/PRESENTATION_ExAdv.tex
manual/PRESENTATION_ExOth.tex
manual/PRESENTATION_ExSyn.tex
manual/PRESENTATION_Intro.tex
manual/PRESENTATION_Prog.tex
manual/presentation.tex
misc/create_vcxsrc.sh
misc/py_wrap_generator.py
passes/cmds/add.cc
passes/cmds/autoname.cc
passes/cmds/blackbox.cc
passes/cmds/check.cc
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passes/cmds/splice.cc
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passes/cmds/trace.cc
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passes/equiv/equiv_add.cc
passes/equiv/equiv_induct.cc
passes/equiv/equiv_make.cc
passes/equiv/equiv_mark.cc
passes/equiv/equiv_miter.cc
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passes/equiv/equiv_remove.cc
passes/equiv/equiv_simple.cc
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passes/fsm/fsm.cc
passes/fsm/fsm_detect.cc
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passes/fsm/fsm_export.cc
passes/fsm/fsm_extract.cc
passes/fsm/fsm_info.cc
passes/fsm/fsm_map.cc
passes/fsm/fsm_opt.cc
passes/fsm/fsm_recode.cc
passes/fsm/fsmdata.h
passes/hierarchy/hierarchy.cc
passes/hierarchy/submod.cc
passes/hierarchy/uniquify.cc
passes/memory/memory.cc
passes/memory/memory_bram.cc
passes/memory/memory_collect.cc
passes/memory/memory_dff.cc
passes/memory/memory_map.cc
passes/memory/memory_memx.cc
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passes/memory/memory_unpack.cc
passes/opt/muxpack.cc
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passes/opt/opt_clean.cc
passes/opt/opt_demorgan.cc
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passes/opt/opt_mem_feedback.cc
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passes/opt/opt_reduce.cc
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passes/opt/pmux2shiftx.cc
passes/opt/rmports.cc
passes/opt/share.cc
passes/opt/wreduce.cc
passes/pmgen/generate.h
passes/pmgen/ice40_dsp.cc
passes/pmgen/ice40_wrapcarry.cc
passes/pmgen/peepopt.cc
passes/pmgen/test_pmgen.cc
passes/pmgen/xilinx_dsp.cc
passes/pmgen/xilinx_srl.cc
passes/proc/proc.cc
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passes/sat/assertpmux.cc
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passes/sat/clk2fflogic.cc
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passes/sat/eval.cc
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passes/techmap/abc.cc
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passes/techmap/aigmap.cc
passes/techmap/alumacc.cc
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passes/techmap/clkbufmap.cc
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passes/techmap/dffinit.cc
passes/techmap/dfflibmap.cc
passes/techmap/extract.cc
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passes/techmap/extract_fa.cc
passes/techmap/extractinv.cc
passes/techmap/flatten.cc
passes/techmap/hilomap.cc
passes/techmap/insbuf.cc
passes/techmap/iopadmap.cc
passes/techmap/libparse.cc
passes/techmap/libparse.h
passes/techmap/lut2mux.cc
passes/techmap/maccmap.cc
passes/techmap/muxcover.cc
passes/techmap/nlutmap.cc
passes/techmap/pmuxtree.cc
passes/techmap/shregmap.cc
passes/techmap/simplemap.cc
passes/techmap/simplemap.h
passes/techmap/techmap.cc
passes/techmap/tribuf.cc
passes/techmap/zinit.cc
passes/tests/test_abcloop.cc
passes/tests/test_autotb.cc
passes/tests/test_cell.cc
techlibs/achronix/speedster22i/cells_arith.v
techlibs/achronix/speedster22i/cells_map.v
techlibs/achronix/speedster22i/cells_sim.v
techlibs/achronix/synth_achronix.cc
techlibs/anlogic/anlogic_eqn.cc
techlibs/anlogic/anlogic_fixcarry.cc
techlibs/anlogic/arith_map.v
techlibs/anlogic/synth_anlogic.cc
techlibs/common/mul2dsp.v
techlibs/common/prep.cc
techlibs/common/simcells.v
techlibs/common/simlib.v
techlibs/common/synth.cc
techlibs/common/techmap.v
techlibs/easic/synth_easic.cc
techlibs/ecp5/arith_map.v
techlibs/ecp5/ecp5_gsr.cc
techlibs/ecp5/synth_ecp5.cc
techlibs/efinix/arith_map.v
techlibs/efinix/efinix_fixcarry.cc
techlibs/efinix/synth_efinix.cc
techlibs/gowin/arith_map.v
techlibs/gowin/synth_gowin.cc
techlibs/greenpak4/greenpak4_dffinv.cc
techlibs/greenpak4/synth_greenpak4.cc
techlibs/ice40/arith_map.v
techlibs/ice40/ice40_braminit.cc
techlibs/ice40/ice40_opt.cc
techlibs/ice40/synth_ice40.cc
techlibs/intel/common/altpll_bb.v
techlibs/intel/common/m9k_bb.v
techlibs/intel/cyclone10lp/cells_arith.v
techlibs/intel/cyclone10lp/cells_map.v
techlibs/intel/cyclone10lp/cells_sim.v
techlibs/intel/cycloneiv/cells_arith.v
techlibs/intel/cycloneiv/cells_map.v
techlibs/intel/cycloneiv/cells_sim.v
techlibs/intel/cycloneive/arith_map.v
techlibs/intel/cycloneive/cells_map.v
techlibs/intel/cycloneive/cells_sim.v
techlibs/intel/max10/cells_arith.v
techlibs/intel/max10/cells_map.v
techlibs/intel/max10/cells_sim.v
techlibs/intel/synth_intel.cc
techlibs/intel_alm/cyclonev/cells_sim.v
techlibs/intel_alm/synth_intel_alm.cc
techlibs/nexus/arith_map.v
techlibs/sf2/arith_map.v
techlibs/sf2/synth_sf2.cc
techlibs/xilinx/abc9_model.v
techlibs/xilinx/arith_map.v
techlibs/xilinx/cells_map.v
techlibs/xilinx/cells_sim.v
techlibs/xilinx/ff_map.v
techlibs/xilinx/lut_map.v
techlibs/xilinx/mux_map.v
techlibs/xilinx/synth_xilinx.cc
techlibs/xilinx/xilinx_dffopt.cc
tests/vloghtb/run-test.sh