projects / mesa.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: aacf194) | patch
intel/genxml: Add Cache Mode SubSlice Register to gen10.xml
authorAnuj Phogat <anuj.phogat@gmail.com>
Fri, 10 Nov 2017 22:22:18 +0000 (14:22 -0800)
committerAnuj Phogat <anuj.phogat@gmail.com>
Tue, 14 Nov 2017 21:23:18 +0000 (13:23 -0800)
commit72a239266b84033e539283d50ca0b3c50e630463
tree6513ea97eabec5aadae41604d815ba368bda53abtree
parentaacf1943c0a13b8ec565d9f256552608d35c3b4acommit | diff
intel/genxml: Add Cache Mode SubSlice Register to gen10.xml

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
src/intel/genxml/gen10.xml diff | blob | history