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(parent: 4b2f2fd) | patch
hdl.ir: don't expose as ports missing domains added via elaboratables.
authorwhitequark <cz@m-labs.hk>
Sat, 3 Aug 2019 16:39:21 +0000 (16:39 +0000)
committerwhitequark <cz@m-labs.hk>
Sat, 3 Aug 2019 16:39:21 +0000 (16:39 +0000)
commit733dfab96acabcb7af7dc469c13632f0f485ec8c
treea10f414b6db76ea85043bc42df455ba11169acb5tree
parent4b2f2fd8fad30b62999ab329b9937f8b2d4bbc28commit | diff
hdl.ir: don't expose as ports missing domains added via elaboratables.

The elaboratable is already likely driving the clk/rst signals in
some way appropriate for the platform; if we expose them as ports
nevertheless it will cause problems downstream.
nmigen/hdl/ir.py diff | blob | history
nmigen/test/test_hdl_ir.py diff | blob | history