i965/vec4: prevent src/dst hazards during 64-bit register allocation

i965/vec4: prevent src/dst hazards during 64-bit register allocation

8-wide compressed DF operations are executed as two separate 4-wide
DF operations. In that scenario, we have to be careful when we allocate
register space for their operands to prevent the case where the first
half of the instruction overwrites the source of the second half.

To do this we mark compressed instructions as having hazards to make
sure that ther register allocators assigns a register regions for the
destination that does not overlap with the region assigned for any
of its source operands.

Reviewed-by: Matt Turner <mattst88@gmail.com>