Refine memory support to deal with general Verilog memory definitions.
authorJim Lawson <ucbjrl@berkeley.edu>
Mon, 1 Apr 2019 22:02:12 +0000 (15:02 -0700)
committerJim Lawson <ucbjrl@berkeley.edu>
Mon, 1 Apr 2019 22:02:12 +0000 (15:02 -0700)
commit73b87e780798fe2c7958b75e4dfddc0dc2169d20
treedb971b48ddb4a763a77e73f96657babf48a35fac
parent22035c20ff071ec5c30990258850ecf97de5d5b3
Refine memory support to deal with general Verilog memory definitions.
backends/firrtl/firrtl.cc