Merge pull request #2396 from YosysHQ/claire/empty-param
authorclairexen <claire@symbioticeda.com>
Fri, 2 Oct 2020 08:16:23 +0000 (10:16 +0200)
committerGitHub <noreply@github.com>
Fri, 2 Oct 2020 08:16:23 +0000 (10:16 +0200)
commit73cd115e0866f2efea622ba5f54d39a621838baa
tree25a25079521ec6aa4c58db1a13c2093751cb2cb0
parenta1a3e686c7bdd8cff139201ee621f10a4d958ed2
parent46f0932c4c61aca3ab5332f99a4a60d110b52191
Merge pull request #2396 from YosysHQ/claire/empty-param

Ignore empty parameters in Verilog module instantiations