x86: template-ize packed/scalar vector floating point insns

x86: template-ize packed/scalar vector floating point insns

The vast majority of vector FP insns comes in single/double pairs. Many
pairs follow certain encoding patterns. Introduce an "sd" template to
reduce redundancy. Similarly, to further cover similarities between
AVX512F and AVX512-FP16, introduce an "sdh" template.

For element-size Disp8 shift generalize i386-gen's broadcast size
determination, allowing Disp8MemShift to be specified without an operand
in the affected templated templates. While doing the adjustment also
eliminate an unhelpful (lost information) diagnostic combined with a use
after free in what is now get_element_size().

Note that in the course of the conversion
- the AVX512F form of VMOVUPD has a stray (leftover) Load attribute
  dropped,
- VMOVSH has a benign IgnoreSize added (the attribute is still strictly
  necessary for VMOVSD, and necessary for VMOVSS as long as we permit
  strange combinations like "-march=i286+avx"),
- VFPCLASSPH is properly split to separate AT&T and Intel syntax forms,
  matching VFPCLASSP{S,D}.