Modified errors into warnings
authorUdi Finkelstein <github@udifink.com>
Tue, 5 Jun 2018 14:44:24 +0000 (17:44 +0300)
committerUnknown <github@udifink.com>
Tue, 5 Jun 2018 15:03:22 +0000 (18:03 +0300)
commit73d426bc879087ca522ca595a8ba921b647fae27
tree29a18815bf8fdae5f20fa4762da31562eabe2829
parent80d9d15f1c4b73ee73172b06fd2c8c55703aea54
Modified errors into warnings
No longer false warnings for memories and assertions
frontends/ast/ast.cc
frontends/ast/ast.h
frontends/ast/simplify.cc
frontends/verilog/verilog_parser.y
tests/various/reg_wire_error.sv