Add testcase for signal used as part input part output
authorEddie Hung <eddie@fpgeh.com>
Sat, 23 Nov 2019 00:52:55 +0000 (16:52 -0800)
committerEddie Hung <eddie@fpgeh.com>
Sat, 23 Nov 2019 00:52:55 +0000 (16:52 -0800)
commit74ea4381362d4f402e7fc262b960e14122128303
tree659e822e4ff958645af8f515b58ae75f906d1311
parent81548d1ef988d10007706c36df5885f8557de74a
Add testcase for signal used as part input part output
tests/simple_abc9/abc9.v