wishbone/wishbone2csr: use wishbone.sel on CSR write.

wishbone/wishbone2csr: use wishbone.sel on CSR write.

CSR write is only done if wishbone.sel != 0. This should avoid the need for 64-bit
CSR alignment on 64-bit CPUs since a 64-bit Wishbone write access targeting only the
32-bit LSB or MSB will be splitted in 2x32-bit accesses: one with sel=0xf, one with sel=0.