projects / nmigen.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 28a22e4) | patch
vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_trigger wires.
authorwhitequark <whitequark@whitequark.org>
Fri, 6 Nov 2020 01:31:14 +0000 (01:31 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 31 Dec 2021 15:20:13 +0000 (15:20 +0000)
commit75e8830de406ba77f07f3aece0baa12ba93a3e67
tree7af199e6b9196ee0a3657a6b200137f7cd046cbctree
parent28a22e440094a25e8756739ec042ccbb8842eaedcommit | diff
vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_trigger wires.

These only matter in simulation and after conversion to Verilog.
During synthesis they cause Yosys to produce warnings:

  Warning: Wire $verilog_initial_trigger has an unprocessed 'init' attribute.
nmigen/vendor/lattice_ecp5.py diff | blob | history
nmigen/vendor/lattice_ice40.py diff | blob | history