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(parent: b2b694d) | patch
sigh, I-DCT had to reverse the order of middle loop to stop
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 29 Jul 2021 19:52:29 +0000 (20:52 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 29 Jul 2021 19:52:29 +0000 (20:52 +0100)
commit76378eb2c4f9b71fcfefa18239197b89230f7ae1
treefa0d17fd15df7ac7f557e7226695e6524fe09733tree
parentb2b694dcaf0a61e91874e5e13ce3d70be6c1d90fcommit | diff
sigh, I-DCT had to reverse the order of middle loop to stop
overwrite-accumulation of iterative sum
src/openpower/decoder/isa/fastdct-test.py diff | blob | history
src/openpower/decoder/isa/fastdctlee.py diff | blob | history