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(parent: 73dbffe) | patch
soc: cores: add up5kspram module
authorWilliam D. Jones <thor0505@comcast.net>
Thu, 20 Jun 2019 18:12:46 +0000 (11:12 -0700)
committerSean Cross <sean@xobs.io>
Thu, 20 Jun 2019 18:12:46 +0000 (11:12 -0700)
commit7656f54d0a1e44fb53a366b0b5030b4c8b7ad4df
treea98b9b97105b1d26a727bc55c3664702bd672a7ctree
parent73dbffe8f209313297549825f7b45d663230e798commit | diff
soc: cores: add up5kspram module

The ICE40UP5K has 128 kB of SPRAM that's designed to be used
as memory for a softcore.  This memory is actually 4 16-bit
chunks that we can gang together to give us either 64 kB or
128 kB.

Add a module that will allow us to use this memory in an ICE40.

Signed-off-by: Sean Cross <sean@xobs.io>
litex/soc/cores/up5kspram.py [new file with mode: 0644] blob