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(parent: f2c9f13) | patch
radv: Use correct flush bits for flushing L2 during CB/DB flushes.
authorBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Thu, 4 Jan 2018 01:11:51 +0000 (02:11 +0100)
committerBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Thu, 4 Jan 2018 18:35:36 +0000 (19:35 +0100)
commit76daa30e4a0d3dfe04c5b79fcdfba17fb1656ccd
treef78635ef076cf4db6530389e5da75ef55591a048tree
parentf2c9f13ec2fdab99f5aa7f32845ee94dd1942fe9commit | diff
radv: Use correct flush bits for flushing L2 during CB/DB flushes.

Copied from radeonsi.

Putting in the correct metadata flush commands for eventually not
flushing L2 on CB/DB switch.

Does not remove the need for V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
at the moment.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
src/amd/vulkan/si_cmd_buffer.c diff | blob | history