Add Verilog "automatic" keyword (ignored in synthesis)
authorClifford Wolf <clifford@clifford.at>
Thu, 23 Nov 2017 07:48:17 +0000 (08:48 +0100)
committerClifford Wolf <clifford@clifford.at>
Thu, 23 Nov 2017 07:51:38 +0000 (08:51 +0100)
commit777f2881d880c7690c33821a90c990a8cebd275d
treec0b06a2395d71403d670f6ae0ddbb3bf7e844a51
parent5b6e52118c09bb5967efc2bc2ebe53b9608bad89
Add Verilog "automatic" keyword (ignored in synthesis)
frontends/verilog/verilog_lexer.l
frontends/verilog/verilog_parser.y