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(parent: c4724ca) | patch
arch-arm: Fix decoding of LDFF1x scalar plus scalar
authorAdrià Armejach <adria.armejach@bsc.es>
Wed, 18 Dec 2019 14:40:17 +0000 (15:40 +0100)
committerAdria Armejach <adria.armejach@gmail.com>
Thu, 19 Dec 2019 11:46:41 +0000 (11:46 +0000)
commit77b6f50ce382b37801c63f8a0d06c02bedbfcafa
treefaa6eed9f0e4df8dd400b623ce7d7dfefda1effctree
parentc4724cac6b75ae9a9f32715f1acfa2d20dcd6fcccommit | diff
arch-arm: Fix decoding of LDFF1x scalar plus scalar

First-faulting loads do allow Rm == 0x1f.

Change-Id: Ib9bcb55e126653813fdbb7c29970af23a2471ebb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23803
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/isa/formats/sve_2nd_level.isa diff | blob | history