git.libre-soc.org Git - riscv-isa-sim.git/commit

author	Andrew Waterman <waterman@eecs.berkeley.edu>
	Tue, 14 Jan 2014 00:42:02 +0000 (16:42 -0800)
committer	Andrew Waterman <waterman@eecs.berkeley.edu>
	Tue, 14 Jan 2014 00:42:02 +0000 (16:42 -0800)
commit	77f281580773fe5217ae40bcf8a0f8bc05c28ded
tree	79885362aa51ce842ec912ba4523f36620b1dce8	tree
parent	7f457c47b339cc7c79f56bb277ed8ed989e88ae1	commit \| diff

Improve performance for branchy code

We now use a heavily unrolled loop as the software I$, which allows the
host machine's branch target prediction to associate target PCs with
unique-ish host PCs.

14 files changed:

Makefile.in		diff \| blob \| history
riscv/decode.h		diff \| blob \| history
riscv/encoding.h		diff \| blob \| history
riscv/gen_icache	[new file with mode: 0755]	blob
riscv/htif.cc		diff \| blob \| history
riscv/htif.h		diff \| blob \| history
riscv/interactive.cc		diff \| blob \| history
riscv/mmu.cc		diff \| blob \| history
riscv/mmu.h		diff \| blob \| history
riscv/processor.cc		diff \| blob \| history
riscv/processor.h		diff \| blob \| history
riscv/riscv.mk.in		diff \| blob \| history
riscv/sim.cc		diff \| blob \| history
riscv/sim.h		diff \| blob \| history

Simple-V augmented version of spike

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