Make sure to translate Debug RAM addresses also.
authorTim Newsome <tim@sifive.com>
Sat, 23 Apr 2016 17:40:23 +0000 (10:40 -0700)
committerTim Newsome <tim@sifive.com>
Mon, 23 May 2016 19:12:11 +0000 (12:12 -0700)
commit78332ffbafeae5e9079bfc69ff136c5d24644a4c
tree8bc0b585669a3c58e74d839fba2aeac9b813b3f4
parentdf640b0cacf4ac6903b21c28e23fd9ef6861f94f
Make sure to translate Debug RAM addresses also.
riscv/decode.h
riscv/sim.cc