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(parent: b980553) | patch
anv/cnl: Don't write to Cache Mode Register 1 on gen10+
authorAnuj Phogat <anuj.phogat@gmail.com>
Wed, 14 Jun 2017 00:01:16 +0000 (17:01 -0700)
committerAnuj Phogat <anuj.phogat@gmail.com>
Fri, 23 Jun 2017 18:16:00 +0000 (11:16 -0700)
commit7896dee349bf747f5c03a9f5206a548b7482e72c
tree280a0fa15bac050299f3fe3ee94d4cf73576a911tree
parentb98055330932a19997e68f2c935b0c7dfd90d9c1commit | diff
anv/cnl: Don't write to Cache Mode Register 1 on gen10+

For PartialResolveDisableInVC field recommendation is to
always set this to 0 and that's the default value of the bit.
So, we have nothing left to write to CACHE_MODE_1.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/intel/vulkan/genX_state.c diff | blob | history