xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v
authorEddie Hung <eddie@fpgeh.com>
Wed, 4 Mar 2020 18:32:51 +0000 (10:32 -0800)
committerEddie Hung <eddie@fpgeh.com>
Wed, 4 Mar 2020 19:31:12 +0000 (11:31 -0800)
commit78d4fff69d09f46f1777213116f09826ba008991
treeea8424b1474f0967926feb637352f7026a69bae5
parent968956badb977984133b00c38d0a08f3e2d0b854
xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v
techlibs/xilinx/abc9_map.v
techlibs/xilinx/abc9_model.v