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(parent: 814ffde) | patch
back.rtlil: refuse to create extremely large wires.
authorwhitequark <whitequark@whitequark.org>
Mon, 13 Apr 2020 16:38:36 +0000 (16:38 +0000)
committerwhitequark <whitequark@whitequark.org>
Mon, 13 Apr 2020 16:38:36 +0000 (16:38 +0000)
commit792f35ac8fed74904ae08dc48cbbc155b04936c3
treeaee44e5facbf60b625075f3f83eaf7c9f2997885tree
parent814ffde6fbf38598c7db31dbea1414d6d5624ecbcommit | diff
back.rtlil: refuse to create extremely large wires.

Such wires are likely to trigger pathological behavior in Yosys and,
if applicable, other toolchains that consume Verilog converted from
RTLIL.

Fixes #341.
nmigen/back/rtlil.py diff | blob | history