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(parent: 69468d5) | patch
More progress on Firrtl backend.
authorAdam Izraelevitz <azidar@gmail.com>
Tue, 22 Nov 2016 01:28:17 +0000 (17:28 -0800)
committerAdam Izraelevitz <azidar@gmail.com>
Mon, 13 Feb 2017 19:17:53 +0000 (11:17 -0800)
commit794cec00166f46a3ea8480377ee7f773884a8f5d
tree6f106d56447804bcc14fc86a5e67ed6cdac5a88ctree
parent69468d5a16f87616af9c7f084f6ff247f3513050commit | diff
More progress on Firrtl backend.

Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a
simple rocket-chip design.
backends/firrtl/firrtl.cc diff | blob | history
backends/firrtl/test.sh diff | blob | history
backends/firrtl/test.v diff | blob | history