generic_platform: do not create clock domains during Verilog conversion
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Mon, 18 Mar 2013 17:44:58 +0000 (18:44 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Mon, 18 Mar 2013 17:44:58 +0000 (18:44 +0100)
commit797411c1a9bc0c0a90a0d0cb0ed867d3bb7c12ee
treead2ee6187f9954d96a10923c5ebc1e06a1d11582
parent4bf31902441d8713a8c24dfbe596843dbaa5562a
generic_platform: do not create clock domains during Verilog conversion
mibuild/generic_platform.py