add twin src and dest flen instruction testing
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Nov 2018 13:45:56 +0000 (13:45 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Nov 2018 13:45:56 +0000 (13:45 +0000)
commit797a6591efcb401fb170399f3290d8941b518c98
treedd2a46079e140d2f408cb069f81b8e92b7c61ca1
parent93b790ce3175b9cbe3d688bf33c0fd8289ddeb39
add twin src and dest flen instruction testing

WRITE_FREG and READ_FREG need different flen inputs.  start differentiating
id_regs.py
riscv/insn_template_sv.cc
riscv/sv.cc
riscv/sv_decode.h
riscv/sv_insn_redirect.cc