Corrected spelling mistakes found by lintian
authorRuben Undheim <ruben.undheim@gmail.com>
Sat, 6 Sep 2014 06:47:06 +0000 (08:47 +0200)
committerRuben Undheim <ruben.undheim@gmail.com>
Sat, 6 Sep 2014 06:47:06 +0000 (08:47 +0200)
commit79cbf9067c07ed810b3466174278d77b9a05b46d
treeb546123251d39df2ffd115fb0b8a08e57e7cf538
parent01ef34c147dd3e3e3d13864f9c726727a4013207
Corrected spelling mistakes found by lintian
22 files changed:
Makefile
backends/blif/blif.cc
frontends/ast/simplify.cc
frontends/verific/build_amd64.txt
frontends/verific/verific.cc
frontends/vhdl2verilog/vhdl2verilog.cc
kernel/register.cc
libs/minisat/Solver.h
manual/CHAPTER_Prog/stubnets.cc
manual/CHAPTER_Techmap.tex
manual/CHAPTER_Verilog.tex
manual/command-reference-manual.tex
manual/manual.tex
passes/cmds/scc.cc
passes/cmds/select.cc
passes/cmds/splice.cc
passes/cmds/splitnets.cc
passes/fsm/fsm_recode.cc
passes/hierarchy/hierarchy.cc
passes/memory/memory_share.cc
passes/opt/opt_clean.cc
passes/sat/sat.cc