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(parent: 6de7e15) | patch
replace Makefile with make.py (will enable verilog rtl generation for integration...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Sat, 17 Jan 2015 13:17:31 +0000 (14:17 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 19 Jan 2015 08:45:34 +0000 (09:45 +0100)
commit79dbb6da4b4d89ee06cc032fbcc125d7077858b1
tree31f4520abd1dfb4561dbeef50badda4c079911e3tree
parent6de7e15a0c9f475db6edac7e59d5923d1f0c7661commit | diff
replace Makefile with make.py (will enable verilog rtl generation for integration with standard flows)
README diff | blob | history
build/.keep_me [new file with mode: 0644] blob
make.py [new file with mode: 0644] blob
targets/bist_kc705.py diff | blob | history