projects / yosys.git / commit
| author | Eddie Hung <eddie@fpgeh.com> | |
| Mon, 22 Apr 2019 19:14:37 +0000 (12:14 -0700) | ||
| committer | Eddie Hung <eddie@fpgeh.com> | |
| Mon, 22 Apr 2019 19:14:37 +0000 (12:14 -0700) | ||
| commit | 79fb291dbedbb6cf582925329e8140cbc7e502a9 | |
| tree | 7cccf0d21f1ac4246f6a4038e8e806b22b931411 | tree |
| parent | 4cfef7897f4bac285853bf0f08ae366523ae76b4 | commit | diff |
| techlibs/xilinx/Makefile.inc | diff | blob | history | |
| techlibs/xilinx/abc.box | [new file with mode: 0644] | blob |
| techlibs/xilinx/abc.lut | [new file with mode: 0644] | blob |
| techlibs/xilinx/cells.box | [deleted file] | blob | history |
| techlibs/xilinx/cells.lut | [deleted file] | blob | history |
| techlibs/xilinx/cells_box.v | [deleted file] | blob | history |
| techlibs/xilinx/cells_sim.v | diff | blob | history | |
| techlibs/xilinx/synth_xilinx.cc | diff | blob | history |