genxml: Add L3 Cache Control register definitions
authorJordan Justen <jordan.l.justen@intel.com>
Thu, 24 Mar 2016 07:29:50 +0000 (00:29 -0700)
committerJordan Justen <jordan.l.justen@intel.com>
Fri, 25 Mar 2016 06:49:53 +0000 (23:49 -0700)
commit7a03fb9ccb3f8a94ec697bc6ebed8c5f859c8b8e
tree98dd079f8fa3411f6f25931679084ae2866a6ea5
parentd353ba8f5fee23e9d9c8165b6cbfaba33e19ace6
genxml: Add L3 Cache Control register definitions

Based on intel_reg.h (5912da45a69923afa1b7f2eb5bb371d848813c41)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
src/intel/genxml/gen7.xml
src/intel/genxml/gen75.xml
src/intel/genxml/gen8.xml
src/intel/genxml/gen9.xml