Fixed parsing of empty positional cell ports
authorClifford Wolf <clifford@clifford.at>
Mon, 25 Jul 2016 10:48:03 +0000 (12:48 +0200)
committerClifford Wolf <clifford@clifford.at>
Mon, 25 Jul 2016 10:48:03 +0000 (12:48 +0200)
commit7a67add95d3d2f3293f84e38b891024d6444d2a4
treef5d4107d03135858f5ca76d1fcd4efd8501c1184
parentb1c432af5613b0e5817ccc35bb081737dfcb6867
Fixed parsing of empty positional cell ports
frontends/verilog/verilog_parser.y