fastmodel: Add an address translation mechanism to the ThreadContext.
authorGabe Black <gabeblack@google.com>
Sat, 19 Oct 2019 00:08:03 +0000 (17:08 -0700)
committerGabe Black <gabeblack@google.com>
Tue, 17 Dec 2019 23:17:28 +0000 (23:17 +0000)
commit7a70cbad802d76b0321d8ec070f72d2f48a3ae11
tree8fb32c22478842ddb6e5900d1c6734aaef7c8766
parentcec93b49359eec5f53dd8c201dc33892e9e376e1
fastmodel: Add an address translation mechanism to the ThreadContext.

This will be used by the TLB to do the actual translation.
Unfortunately there isn't a great way to tell what translation type to
use, so we just go through all of them for now. The ARM subclass might
specialize and figure out which address spaces to use based on control
register state.

Change-Id: Id1fcad66554acf9d69af683917b3c2834f825da0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22118
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/fastmodel/iris/arm/thread_context.cc
src/arch/arm/fastmodel/iris/arm/thread_context.hh
src/arch/arm/fastmodel/iris/thread_context.cc
src/arch/arm/fastmodel/iris/thread_context.hh