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(parent: 0c7e0bf) | patch
Fix ECP5PLL VCO frequency range
authorXiretza <xiretza@xiretza.xyz>
Mon, 24 Feb 2020 13:39:44 +0000 (14:39 +0100)
committerXiretza <xiretza@xiretza.xyz>
Mon, 24 Feb 2020 13:39:59 +0000 (14:39 +0100)
commit7a87d4e262436b9f693a5a1fce29c36f7247b8d9
tree820cb122c80a0b96ee816b304c10ab0ace09422ftree
parent0c7e0bf02571230aa48e75d99ee1ccc73ccf59bccommit | diff
Fix ECP5PLL VCO frequency range

See https://www.latticesemi.com/view_document?document_id=50461 ("ECP5
and ECP5-5G Family Data Sheet"), section 3.19 "sysCLOCK PLL Timing".
litex/soc/cores/clock.py diff | blob | history