sort out CR RM Mode (sz/dz bits moved, consistent)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 18 Sep 2022 17:31:35 +0000 (18:31 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 18 Sep 2022 17:31:35 +0000 (18:31 +0100)
commit7a8f7300cf6ee58496219df61452cff13a9da88e
tree56f690bec7c9a3c925e99a94d303da8d616c8b35
parent73f930e2974d5c674e436cf8bc79f6984c94a35b
sort out CR RM Mode (sz/dz bits moved, consistent)
src/openpower/decoder/power_insn.py