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(parent: 1321c45) | patch
back.rtlil: lower maximum accepted wire size.
authorwhitequark <whitequark@whitequark.org>
Wed, 22 Jul 2020 14:43:44 +0000 (14:43 +0000)
committerwhitequark <whitequark@whitequark.org>
Wed, 22 Jul 2020 14:43:44 +0000 (14:43 +0000)
commit7aedb3e77045e865ea8e676b4a6616d03599a3ad
treec1ac8601e0215a0eab9a62e12575b55d4fffbeb8tree
parent1321c4591da619441dcea25c0bbfa3b224da3129commit | diff
back.rtlil: lower maximum accepted wire size.

In practice wires of just 100000 bits sometimes have unacceptable
performance with Yosys, so stick to Verilog's minimum limit of 65536
bits.
nmigen/back/rtlil.py diff | blob | history