Merge pull request #2463 from georgerennie/fix_verilog_frontend_auto_defines
authorClaire Xen <claire@symbioticeda.com>
Tue, 1 Dec 2020 11:31:34 +0000 (12:31 +0100)
committerGitHub <noreply@github.com>
Tue, 1 Dec 2020 11:31:34 +0000 (12:31 +0100)
commit7b0cfd5c36af774ae255459d4ef0fa0934929902
treecf7fce2a15b877ca8fbbaa2dba24c6d35e4814bb
parentef5b2777c3a6e3abaa0aa24012bd47e2a2c8a4db
parentc1f6ce8b33b1c06a4e38b621e27876d5715eb26d
Merge pull request #2463 from georgerennie/fix_verilog_frontend_auto_defines

Fix SYNTHESIS always being defined in Verilog frontend