Fix Iverilog simulation
authorJean THOMAS <git0@pub.jeanthomas.me>
Wed, 1 Jul 2020 16:57:52 +0000 (18:57 +0200)
committerJean THOMAS <git0@pub.jeanthomas.me>
Wed, 1 Jul 2020 16:57:52 +0000 (18:57 +0200)
commit7b509938d7fbffb96de8223f3e676d75a70d0d5f
tree408f052659630b72d2071366c9f597bbc8878b4a
parent3485ee35c558ecf966e480c71a31f21db8825bd4
Fix Iverilog simulation
gram/simulation/icarusecpix5platform.py
gram/simulation/runsimsoc.sh
gram/simulation/simcrgtb.v
gram/simulation/simsoc.py
gram/simulation/simsoc.ys [new file with mode: 0644]