xilinx: consider DSP48E1.ADREG
authorEddie Hung <eddie@fpgeh.com>
Wed, 4 Mar 2020 20:04:02 +0000 (12:04 -0800)
committerEddie Hung <eddie@fpgeh.com>
Wed, 4 Mar 2020 20:04:02 +0000 (12:04 -0800)
commit7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f
treeab1520d1aa2b19eb44cb46611b425431567ca0b0
parent512596760b947a9ac9088856490970d0930dd951
xilinx: consider DSP48E1.ADREG
techlibs/xilinx/abc9_map.v
techlibs/xilinx/abc9_model.v
techlibs/xilinx/abc9_unmap.v
techlibs/xilinx/cells_sim.v