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(parent: f4b2358) | patch
intel: Correct the BDW surface state size
authorNanley Chery <nanley.g.chery@intel.com>
Tue, 7 Mar 2017 19:17:05 +0000 (11:17 -0800)
committerNanley Chery <nanley.g.chery@intel.com>
Mon, 20 Mar 2017 16:43:44 +0000 (09:43 -0700)
commit7c50f9903f58ef04ff393505a383d06f499f1fdc
tree4ece2ce95847ba8ab4465526531da36f1e0995a0tree
parentf4b23589da8ad395b6d5bc968502d8128a8bd8c5commit | diff
intel: Correct the BDW surface state size

The PRMs state that this packet is 16 DWORDS long. Ensure that the last
three DWORDS are zeroed as required by the hardware when allocating a
null surface state.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
src/intel/isl/isl.c diff | blob | history
src/mesa/drivers/dri/i965/gen8_surface_state.c diff | blob | history