arch-riscv: set MaxMiscDestRegs to 2
authorAlec Roelke <alec.roelke@gmail.com>
Fri, 29 Nov 2019 20:41:19 +0000 (15:41 -0500)
committerAlec Roelke <alec.roelke@gmail.com>
Sun, 8 Dec 2019 15:17:51 +0000 (15:17 +0000)
commit7c961a57f482e2b37eb38403f3374990dcf85032
tree05c09fe01e20350dcc7dc4510020795a08f26da7
parent3b9395cd02c9611f32cea1abead058fd4f171726
arch-riscv: set MaxMiscDestRegs to 2

In an earlier patch, the FCSR was split into its two components, FRM and
FFLAGS, causing explicit writes to FCSR to incur two CSR writes. With
the O3 CPU model, which defers them both to later, this creates a bug
where an assertion that the number of CSR writes must be less than
MaxMiscDestRegs fails because that constant is 1. This patch sets it to
2 so the O3 CPU is compatible with this scheme.

Change-Id: Ic3413738c4eebe9f127980d0d0af5033d18468e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23220
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/riscv/registers.hh