projects / gram.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: ffdcef6) | patch
Wire up missing CRG / DDR3 clock control / reset signals
authorRaptor Engineering Development Team <support@raptorengineering.com>
Sat, 9 Apr 2022 20:00:47 +0000 (15:00 -0500)
committerRaptor Engineering Development Team <support@raptorengineering.com>
Sat, 9 Apr 2022 20:00:47 +0000 (15:00 -0500)
commit7cb3e51d2d2c7e1d71fc9c991697e1270f60358b
treeba53a19a179fbc084ec8d4ab926126626cbdc426tree
parentffdcef6b591e73932a97278e011834c8303731cccommit | diff
Wire up missing CRG / DDR3 clock control / reset signals

Swap DELAYF for DELAYG on DQ lines
examples/ecp5_crg.py diff | blob | history
gram/phy/ecp5ddrphy.py diff | blob | history