Merge pull request #181 from rubund/input_logic_allowed
authorClifford Wolf <clifford@clifford.at>
Tue, 21 Jun 2016 06:44:20 +0000 (08:44 +0200)
committerGitHub <noreply@github.com>
Tue, 21 Jun 2016 06:44:20 +0000 (08:44 +0200)
commit7cddab0788cadc220ffa098c4ac037362ad6948e
tree8df204605907e01759969afa2386274ea398c620
parent541083cf329addb57117618de41697dd010d07cf
parent545bcb37e8fa569d88374f92aafdcc1004e9b587
Merge pull request #181 from rubund/input_logic_allowed

Allow defining input ports as "input logic" in SystemVerilog