verilog: fix $specify3 check
authorEddie Hung <eddie@fpgeh.com>
Wed, 12 Feb 2020 20:16:01 +0000 (12:16 -0800)
committerEddie Hung <eddie@fpgeh.com>
Thu, 13 Feb 2020 20:42:04 +0000 (12:42 -0800)
commit7cfdf4ffa7698fa40aae401c2b8b159a6e37011a
treec94c86d18749a16b405545aa95718254a350513a
parentcb7bc6a12fee1d948b7f91fd37f326dbd4f5ca47
verilog: fix $specify3 check
frontends/ast/genrtlil.cc
tests/various/specify.v