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(parent: 28d80bd) | patch
global: switch to VexRiscv as the default CPU
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 22 Apr 2019 07:37:00 +0000 (09:37 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 22 Apr 2019 07:41:07 +0000 (09:41 +0200)
commit7d278854d56cd7d9df1632835d22e590c3250540
treec405fe83cb08d7d632c85e9360a20c87f9c7d127tree
parent28d80bd64146f5c11b892515aad27df04c6d8994commit | diff
global: switch to VexRiscv as the default CPU

VexRiscv can now replace LM32 for almost all usecases and we now have better
software support with RISC-V.
README diff | blob | history
litex/soc/integration/soc_core.py diff | blob | history
test/test_targets.py diff | blob | history