intel/fs: Combine adjacent memory barriers
authorCaio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Fri, 21 Feb 2020 18:58:48 +0000 (10:58 -0800)
committerMarge Bot <eric+marge@anholt.net>
Thu, 12 Mar 2020 19:21:36 +0000 (19:21 +0000)
commit7d54b84d49de991188a6a91bbadf00e89654f2c0
tree4a7b0338955f898db670118d0feed83d8924eb6d
parentbf432cd831c789c02f9474f836e3259f2a73abd3
intel/fs: Combine adjacent memory barriers

This will avoid generating multiple identical fences in a row.

For Gen11+ we have multiple types of fences (affecting different
variable modes), but is still better to combine them in a single
scoped barrier so that the translation to backend IR have the option
of dispatching both fences in parallel.

This will clean up redundant barriers from various
dEQP-VK.memory_model.* tests.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3224>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3224>
src/intel/compiler/brw_nir.c