arch-riscv: Add support for compressed extension RV64C
authorAlec Roelke <ar4jc@virginia.edu>
Wed, 14 Jun 2017 21:33:29 +0000 (17:33 -0400)
committerAlec Roelke <ar4jc@virginia.edu>
Tue, 11 Jul 2017 03:45:14 +0000 (03:45 +0000)
commit7e6a35374a944b67868d92ce85b427ea9103ca53
tree0fe3c97c11967468b2c66ce0edbc656d3c485a61
parent63d4005a29dea37e0219444a3de2cdb25289fdfb
arch-riscv: Add support for compressed extension RV64C

This patch adds compatibility with the 64-bit compressed extension to
the RISC-V ISA, RV64C.  Current versions of the toolchain may use
compressed instructions in glibc by default, which can only be
overridden by recompiling the entire toolchain (simply adding
"-march=rv64g" or "-march=rv64imafd" when compiling a binary is not
sufficient to use uncompressed instructions in glibc functions in the
binary).

[Update diassembly generation for new RegId type.]
[Rebase onto master.]

Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4
Reviewed-on: https://gem5-review.googlesource.com/3860
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
src/arch/riscv/decoder.cc
src/arch/riscv/decoder.hh
src/arch/riscv/isa/bitfields.isa
src/arch/riscv/isa/decoder.isa
src/arch/riscv/isa/formats/compressed.isa [new file with mode: 0644]
src/arch/riscv/isa/formats/formats.isa
src/arch/riscv/isa/formats/mem.isa
src/arch/riscv/isa/includes.isa
src/arch/riscv/isa/operands.isa
src/arch/riscv/types.hh