litedram: Add support for Microwatt-initialized controller
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Fri, 8 May 2020 15:09:26 +0000 (01:09 +1000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Sat, 9 May 2020 00:57:18 +0000 (10:57 +1000)
commit7f1f6b852570ed003e425d5737d7570196ce6911
treea8458ee64ff140354f25e2323aec010f9831a88b
parentc5f5f507385dd9d2dad62908c79d911d237a4eda
litedram: Add support for Microwatt-initialized controller

This adds support for initializing the memory controller from microwatt
rather than using a built-in RiscV processor. This might require some
fixes to LiteX and LiteDRAM (they haven't been merged as of this commit
yet).

This is enabled in the shipped generated files and can be changed via
modifying the generator script to pass False to "mw_init"

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
16 files changed:
litedram/gen-src/arty.yml
litedram/gen-src/generate.py
litedram/gen-src/sdram_init/Makefile
litedram/gen-src/sdram_init/include/system.h
litedram/gen-src/sdram_init/libc/include/limits.h [new file with mode: 0644]
litedram/gen-src/sdram_init/main.c
litedram/gen-src/wrapper-mw-init.vhdl
litedram/generated/arty/init-cpu.txt [deleted file]
litedram/generated/arty/litedram-wrapper.vhdl
litedram/generated/arty/litedram_core.init
litedram/generated/arty/litedram_core.v
litedram/generated/nexys-video/init-cpu.txt [deleted file]
litedram/generated/nexys-video/litedram-wrapper.vhdl
litedram/generated/nexys-video/litedram_core.init
litedram/generated/nexys-video/litedram_core.v
soc.vhdl