aarch64: Fix SVE2 BCAX pattern [PR97730]

aarch64: Fix SVE2 BCAX pattern [PR97730]

This patch adds a missing not to the SVE2 BCAX (Bitwise clear and
exclusive or) pattern, fixing the PR. Since SVE doesn't have an
unpredicated not instruction, we need to use a (vacuously) predicated
not here.

To ensure that the predicate is instantiated correctly (to all 1s) for
the intrinsics, we pull out a separate expander from the define_insn.

From the ISA reference [1]:
> Bitwise AND elements of the second source vector with the
> corresponding inverted elements of the third source vector, then
> exclusive OR the results with corresponding elements of the first
> source vector.

[1] : https://developer.arm.com/docs/ddi0602/g/a64-sve-instructions-alphabetic-order/bcax-bitwise-clear-and-exclusive-or

gcc/ChangeLog:

	PR target/97730
	* config/aarch64/aarch64-sve2.md (@aarch64_sve2_bcax<mode>):
	Change to define_expand, add missing (trivially-predicated) not
	rtx to fix wrong code bug.
	(*aarch64_sve2_bcax<mode>): New.

gcc/testsuite/ChangeLog:

	PR target/97730
	* gcc.target/aarch64/sve2/bcax_1.c (OP): Add missing bitwise not
	to match correct bcax semantics.
	* gcc.dg/vect/pr97730.c: New test.